Method for correcting timing for IC tester and IC tester having correcting function using the correcting method

ABSTRACT

A timing correcting method for correcting the timings of an IC tester at low cost, wherein the method uses a probe ( 300 ) for taking out a signal fed to a pin out of the pins of an IC socket ( 203 ) to which an IC to be measured is plugged when the probe is brought into contact with the pin and supplying a correcting pulse to the pin, and the timing of the correcting pulse taken in by a reference comparator (CP-RF) provided in the probe and the timing of a reference correcting pulse applied to an IC socket from a reference driver (DR-RF) provided in the probe are measured by a timing measuring function that the IC tester has, thus performing timing correction.

TECHNICAL FIELD

The present invention relates to a timing calibration method for an ICtester for testing ICs such as memories and an IC tester equipped with acalibration function using the calibration method.

PRIOR ART

FIG. 11 depicts the general outlines of a commonly known IC tester.Reference character TES designates generally the IC tester. The ICtester TES comprises a main controller 111, a pattern generator 112, atiming generator 113, a waveform formatter 114, a logic comparator 115,a driver group 116, a comparator group 117, a failure analysis memory118, a logical amplitude reference voltage source 121, a comparisonreference voltage source 122 and a device power supply 123.

The main controller 111 is formed, in general, by a computer system andoperates under the control of a test program prepared by a user,controlling the pattern generator 112 and the timing generator 113. Thepattern generator 112 generates test pattern data, which is converted bythe waveform formatter 114 to a test pattern signal that has an actualwaveform, and the test pattern signal is provided to and stored in an ICunder test 119 after being voltage-amplified by the driver group 116 toa waveform having an amplitude value set in the logical amplitudereference voltage source 121.

For example, when the IC under test 119 is an IC memory, a responsesignal read out of the IC under test 119 is compared by the comparatorgroup 117 with a reference voltage from the comparison reference voltagesource 122 to decide the logic level (voltage of a logic “H”, voltage ofa logic “L”) of the response signal. The logic level thus decided iscompared by the logic comparator 115 with an expected value that isoutput from the pattern generator 112; if a mismatch is found betweenthe logic level and the expected value, it is decided that the memorycell of the address from which the response signal was read out isfailing, and upon each occurrence of such a failure, the faulty addressis stored in the failure analysis memory 118 for use in deciding, aftercompletion of the test, whether the failed cell is repairable.

The timing generator 113 generates timing that defines the rise and falltiming of the waveform of the test pattern signal that is applied to theIC under test 119, and the timing of a strobe pulse that defines thetiming for logical comparison by the logic comparator 115.

The respective timing is described in the user's prepared program sothat at the user's intended timing the IC under test 119 can be actuatedand tested for normal operation.

A description will be given, with reference to FIG. 12, the generaloutlines of the timing generator 113 and the waveform formatter 114.FIG. 12 depicts the general configurations of the waveform formatter andthe timing generator for generating a one-channel test pattern signal.The waveform formatter 114 can be formed by an S-R flip-flop, which issupplied at its set and reset terminals S and R with set and resetpulses P_(S) and P_(R), respectively, to generate a test pattern signalTS that rises at predetermined timing T1 and falls at predeterminedtiming T2. In FIG. 12 the outputs from clock generators 113A and 113Bare shown to be provided directly to the S-R flip-flop for the sake ofbrevity, but in practice, the connection of the outputs from a pluralityof clock generators to the S-R flip-flop is controlled in real time inaccordance with the waveform mode and pattern data.

The set and reset pulses P_(S) and P_(R) are generated by the pair ofclock generators 113A and 113B. The generation timing of the set andreset pulses P_(S) and P_(R) by the clock generators 113A and 113B isdefined by pieces of delay data DY_(S) and DY_(R) available from a delaydata memory 113C.

The delay data memory 113C is accessed with an address signal that isprovided from an address counter 113D. The address counter 113Dgenerates an address signal whose address is incremented by one for eachtest cycle TS_(RAT) after the start of testing; based on the addresssignal, an address assignment is made for each test cycle TS_(RAT)during the test period, then delay data preset for each test cycleTS_(RAT) is read out, and the read-out delay data is set in the clockgenerators 113A and 113B, which generate the set pulse P_(S) and thereset pulse P_(R) in accordance with the delay data.

FIGS. 13A-13E show how the above operations are carried out. The setpulse P_(S) is generated at timing delayed, by given delay data DY_(S1),behind, for instance, the rise timing of a rate clock RAT that definesthe test cycle TS_(RAT), and generates the reset pulse P_(R) at timingdelayed behind the rise timing of the rate clock RAT by delay dataDY_(R1), thereby generating the test pattern signal TP of a pulse widthcorresponding to the time difference T_(PW) between the set and resetpulses P_(S) and P_(R) (see FIG. 13E). The resolution for setting theset and reset pulses P_(S) and P_(R) is defined by the pulse interval ofa clock CK depicted in FIG. 13B.

From the above it will be understood that the test pattern signal TP canbe set to rise and fall at arbitrary timing within the test cycleTS_(RAT).

Next, the operation of the comparator group 117 will be described. Thecomparator group 117 performs:

(a) an operation of deciding the logic of the response signal from theIC under test 119 by comparing it with a predetermined reference levelat predetermined timing and capturing the decided logical value; and

(b) an operation of measuring the timing of the rise or fall of theresponse output signal TX.

FIGS. 14A-14F are explanatory of the operation (a). In the case of theoperation (a), the comparator sets the timing of a strobe pulse STB atthe timing when the response output signal TX ought to arrive, andcaptures the logical value of the response output signal TX at the settiming of the strobe pulse STB. In the FIG. 14 example, since the strobepulse STB is set in the H-logic period of the response output signal TX,the comparator captures the H logic that is the result of the logicdecision as shown in FIG 14D. Accordingly, when the expected value inthis test cycle is H as depicted in FIG. 14, the result of the logicalcomparison by the logic comparator 115 is decided to be OK (good) asshown in FIG 14F.

FIGS. 15A-15E are explanatory of the operation (b). In the case ofmeasuring the timing of the rise and fall of the response output signalTX, the phase of the strobe pulse STB that is applied to the comparator17 is shifted for each test cycle TS_(RAT) within the range of the testcycle TS_(RAT) or within the range several times longer than the testcycle, the logical value of the comparator output varies at the timingof the strobe pulse, and the rise timing and fall timing of the responseoutput signal are decided based on the timing of the strobe pulse at thetime the state of the logical decision output reverses as depicted inFIG. 14D.

From the description given above with reference to FIGS. 11 to 15, itwill be understood that the conventional IC tester has the capabilitiesof arbitrarily setting the generation timing of the test pattern signaland measuring the timing of the rise and fall of the response outputsignal TX from the IC under test.

The IC tester performs a timing calibration for in-phase application oftest pattern signals to respective pins of the IC under test and atiming calibration for in-phase reading of response output signals fromthe IC under test into the IC tester.

A conventional method of timing calibration adopts a scheme that adjuststhe delay times of variable delay circuits inserted in signal paths ofrespective pins to provide the same delay time on the signal paths.

The following two schemes are used to measure the delay time of thesignal path.

(1) The time of reflection of the signal propagating along the signalpath is measured through utilization of the timing measuring capabilityof the IC tester and the propagation delay time of the signal path iscomputed from the measured time of reflection.

(2) A probe is held in touch with each pin of an IC socket on which theIC under test is mounted, then a calibration pulse applied to each pinof the IC socket is applied via the probe to an oscilloscope to measurethe phase difference between the calibration pulse and a signal of areference phase, and the propagation delay time of each signal path iscalculated from the phase difference.

With the scheme (1), the reflected wave of the calibration pulse is poorin waveform quality. This inevitably decreases the accuracy in detectingthe arrival of the reflected wave, resulting in the accuracy of timingcalibration being low.

With the scheme (2), since the oscilloscope is used to measure the phasedifference between the signal under measurement and the referencesignal, the measurement accuracy is high. Hence, the timing calibrationcan be performed with high accuracy.

With the measuring scheme (2), however, the signal path that permitscalibration is limited specifically to a signal path equipped with adriver capable of sending a signal to the IC socket, and the signal pathwith only the comparator is not subject to measurement by this method.Hence, the signal path with only the comparator requires measuring itspropagation delay time through utilization of the reflected wave asmentioned above in (1). Accordingly, the measuring scheme (2) is high inthe accuracy of the timing calibration for the driver-associated pathbut low in the calibration accuracy for the comparator-associated path,and hence it has the defect of decreased accuracy in timing calibrationas a whole.

Furthermore, the scheme (2) involves the preparation of an oscilloscopethat is not ever necessary for IC testing. A two-input oscilloscope isexpensive which has a configuration that outputs data corresponding tothe phase difference between two signals and sends the data to the ICtester to adjust the delay time of a variable delay circuit. Thus, thismethod requires the preparation of such a costly oscilloscope only fortiming calibration, and hence it is economically disadvantageous.

An object of the present invention is to provide a timing calibrationmethod for an IC tester that reduces the cost for timing calibration andpermits accurate timing calibration irrespective of the driver- orcomparator-associated path, and an IC tester that possesses the functionof implementing the timing calibration method.

DISCLOSURE OF THE INVENTION

The present invention implements a timing calibration throughutilization of the afore-mentioned timing generation and timingmeasurement features which common IC testers have inherently.

According to a first aspect of the present invention, there is provideda timing calibration method for an IC tester which uses a probe with areference comparator, said method comprising the steps of:

(a) selectively contacting respective pins of an IC socket one afteranother by said probe from outside;

(b) applying a calibration pulse from a driver of said IC tester to eachpin of said IC socket;

(c) capturing said calibration pulse applied from said driver to saideach pin by said reference comparator of said probe at the timing of areference strobe pulse that is provided to said reference comparator;

(d) calculating a deviation between the timing of said calibration pulseand the timing of said reference strobe pulse; and

(e) adjusting the delay time of a variable delay circuit provided ineach signal path of said driver so that said deviation takes apredetermined value.

According to a second aspect of the present invention, there is provideda timing calibration method which uses a probe with a reference driver,said method comprises the steps of:

(a) selectively contacting respective pins of an IC socket one afteranother by said probe from outside;

(b) applying a reference calibration pulse from said reference driver toeach pin of said IC socket;

(c) capturing said reference calibration pulse applied from saidreference driver to each pin by each comparator of said IC tester at thetiming of a strobe pulse that is provided to said each comparator;

(d) calculating a deviation between the timing of said referencecalibration pulse and the timing of said strobe pulse; and

(e) adjusting the delay time of a timing calibrating variable delaycircuit inserted in a signal path of said strobe pulse so that saiddeviation takes a predetermined value.

According to a third aspect of the present invention, there is providedIC tester equipped with a calibration function which has drivers eachprovided in correspondence with one of pins of an IC socket on which ICsunder test are placed, for applying a test pattern signal to the inputterminal of each IC under test, and a comparator for capturing thelogical value of a response output signal provided at the outputterminal of each IC under test, and decides whether the response signalcaptured by said comparator coincides with a predetermined expectedvalue to test said IC under test for normal operation, said IC testercomprising:

a probe for selectively contacting the pins of said IC socket one afteranother;

a reference comparator mounted in said probe, for capturing a signalapplied to the pin of said IC socket contacted by said probe at thetiming of a reference strobe pulse;

a driver variable delay circuit provided in the signal path of each ofsaid drivers, for adjusting the delay time of the signal to be providedto the pin of said IC socket;

a strobe variable delay circuit provided in the signal path of thestrobe pulse to be provided to said each driver, for adjusting the delaytime of said strobe pulse; and

calibration control means for comparing the logical value of the signalcaptured by said reference comparator with an expected value and forcontrolling said driver variable delay circuit so that the phase of acalibration pulse applied to the pin of said IC socket from said eachdriver coincides with reference timing of said reference strobe pulse.

According to the present invention, since it is decided whether thetiming of the calibration pulse captured from the IC socket into theprobe coincides with reference timing through utilization of a timingmeasuring function that the IC tester inherently possesses, anyparticular expensive jig, such as an oscilloscope, need not be providedoutside the tester. Hence, the timing calibration can be performed atlow cost.

Further, according to the present invention, the reference driver ismounted in the probe and the calibration pulse of a reference phase isapplied from the reference driver to the pin of the IC socket with whichthe probe is in contact. The calibration pulse is captured by thecomparator of the IC tester via a cable or the like from the pin of theIC socket.

The comparator of the IC tester measures the timing of the calibrationpulse while sequentially shifting the phase of the strobe pulse. Basedon the timing measured result, the delay time of a variable delaycircuit inserted in the signal path of the strobe pulse is set so thatthe timing of, for example, the leading edge of the calibration pulsecoincides with reference timing, with which the timing calibration ofthe comparator is completed.

As described above, the present invention utilizes the timing measuringcapability of the IC tester to perform timing calibration, and hencedoes not require any particular jig. This provides an advantage that thecost for timing calibration is very low.

Moreover, the present invention utilizes a direct wave as a signal formeasuring the propagation delay time of the signal path, and hence theinvention provides highly accurate measurement results. This also leadsto highly accurate timing calibration.

Besides, according to the present invention, the probe is mounted on anautomatic positioning device (robot), by which the probe isautomatically brought into contact with each pin of the IC socket. Thisproduces the advantage of automated timing calibration as well.

Furthermore, since the present invention offer a timing calibrationdevice that has a plurality of probes and simultaneously performs timingcalibration of driver- and comparator-associated signal paths connectedto a plurality of IC sockets, it is also possible to sharply reduce thetime for calibration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for explaining an embodiment of the IC testeraccording to the present invention.

FIG. 2 is a block diagram for explaining an example of the internalconfiguration of a probe shown in FIG. 1.

FIGS. 3A-3D are waveform diagrams for explaining the calibration methodaccording to the present invention.

FIG. 4 is a block diagram for explaining another calibration methodaccording to the present invention.

FIG. 5 is a block diagram illustrating another example of the internalconfiguration of the probe depicted in FIG. 2.

FIG. 6 is a block diagram for explaining a modified form of theembodiment depicted in FIG. 5.

FIG. 7 is a perspective view for explaining a short pad for calibrationuse that is suitable for application to the embodiment depicted in FIG.6.

FIG. 8 is a block diagram for explaining an example of the internalconfiguration of a calibration controller shown in FIG. 4.

FIGS. 9A-9F are timing charts for explaining the operation of a variabledelay circuit used in the calibration controller depicted in FIG. 8.

FIG. 10 is a block diagram for explaining an example of a fractionaldelay time generating part forming the variable delay circuit depictedin FIG. 8.

FIG. 11 is a block diagram for explaining the general configuration ofan IC tester.

FIG. 12 is a block diagram for explaining the general outlines of atiming generator used in the IC tester depicted in FIG. 11.

FIGS. 13A-13E are waveform diagrams for explaining the operation of thetiming generator shown in FIG. 12.

FIGS. 14A-14F are waveform diagrams for explaining one of functions of acomparator used in the IC tester depicted in FIG. 11.

FIGS. 15A-15E are waveform diagrams for explaining another function ofthe comparator.

BEST MODE FOR CARRYING OUT THE INVENTION

In FIG. 1 there is illustrated an embodiment of the IC tester equippedwith the timing calibration feature according to the present invention.Embodiments of this IC tester will hereinafter be described togetherwith the timing calibration method according to the present invention.

In FIG. 1, reference numeral 100 denotes an IC tester, 200 a test head,300 a probe proposed by the present invention, and 400 an automaticpositioning device that supports the probe 300 and performs positioning.

The IC tester comprises a timing/pattern generator 110, a timingcalibration delay time setting part 120, pin electronics 130 and acalibration controller 140. The calibration controller 140 comprises atiming decision means 150 and variable delay circuits DY1 and DY2. Thetiming decision device is shown which is specifically provided in thepresent invention.

The test head 200 comprises a mother board 201, a socket board 202disposed above the mother board 201, and an IC socket 203 mounted on thesocket board 202. The pin electronics 130 may also be installed on themother board 201. In this embodiment, during calibration a contact board204 is placed on the surface of the IC socket 203 in place of an ICunder test (not shown, in particular), and each pin of the IC socket 203is electrically connected to the corresponding one of contact pads (notshown) formed on the surface of the contact board 204, establishingelectrical contact between each pin of the IC socket 203 and the probe300 via the contact board 204. Accordingly, FIG. 1 depicts the IC testerin the state of calibration.

Conventionally, the probe 300 is formed only by a mere contactor, and acable 301 connected to the probe 300 is connected to an oscilloscope(not shown); a calibration pulse from each driver DR in the pinelectronics 130 is detected by the probe 300 and input via the cable 301to the oscilloscope for measuring the phase of the calibration pulse.

As will be described later on with reference to FIG. 2, the presentinvention features such a configuration as described later on withreference to FIG. 2 in which: no oscilloscope is used; a referencedriver and a reference comparator are provided in the probe 300; thephases of the calibration pulses from the respective drivers DR of thepin electronics 130 are detected by the reference comparator; it ischecked by the timing decision device 140 as to whether the calibrationpulses lead or lag relative to each other; and, based on the checkresult, the amounts of delay of the variable delay circuits DY arecontrolled so that the calibration pulses are timed to each other.

Further, a reference calibration pulse of reference timing is providedfrom the timing/pattern generator 110 to the probe 300, then thereference calibration pulse is input via the reference driver of theprobe 300 to each comparator CP in the pin electronics 130, and theapplication of the strobe pulse to the comparator CP is timed to theleading edge (generally, a 50% position on the leading edge) of thereference calibration pulse, with which the timing calibration of thecomparator CP is completed.

In FIG. 1 only one IC socket 203 is shown, but in practice, for example,12, 24, or 48 IC sockets are placed on the socket board 202, and ICs tobe tested are placed on the respective IC sockets 203 at one time andtested at the same time.

FIG. 2 depicts an example of the internal configuration of the probe 300proposed in the present invention. The probe 300 is mounted on theautomatic positioning device 400, by which the probe 300 is moved in theX-Y direction along the top surface of the socket board 202 and, at theposition of a desired pin (at the position of an electrical pad formedon the surface of the contact board 204), the probe 300 is moved in theZ direction (vertically to the top surface of the contact board 204 tobring spring contacts 302 and 303 resiliently projecting out of theprobe 300 into engagement with the desired electrical pad. In theillustrated example the spring contact 302 is for contact with theground potential and the contact 303 is for contact with a signal line.

The contact 303 for contact with the signal line is connected to theoutput terminal of a reference driver DR-RF and the input terminal of areference comparator CP-RF both provided in the probe 300. Connected tothe input terminal of the reference driver DR-RF is a referencecalibration pulse supply line 304. Connected to the output terminal ofthe reference comparator CP-RF is a reference comparator output line305. Further, a reference strobe pulse supply line 306 is connected to astrobe pulse supply terminal of the reference comparator CP-RF.

The reference calibration pulse supply line 304, the referencecomparator output line 305 and the reference strobe pulse supply line306 are bundled in the cable 301 and connected to the IC tester 100,wherein the reference calibration pulse supply line 304 and thereference strobe pulse supply line 306 are connected to thetiming/pattern generator 110 via the timing calibrating variable delaycircuits DY1 and DY2 of the calibration controller 140 as shown in FIG.1.

The reference comparator output line 305 is connected to the one inputterminal of the timing decision device 150 to input thereto the logicalvalue detected by the reference comparator CP-RF. An expected value isprovided to the other input terminal of the timing decision device 150from the timing/pattern generator 110, and a logical comparison is madebetween the expected value and the reference comparator output to decidewhether the timing of the output from the pin electronics 130 coincideswith the reference timing.

More specifically, for example, in the case where an “H” logic value isgiven as the expected value and the result of the logical decision forthe reference comparator CP-RF of the probe 300 does not coincide withthe expected value “H” at the timing of the reference strobe pulse, thetiming decision means 150 increases the delay of the variable delaycircuit DY2 by a fixed value and repeats the comparison between thelogical decision result and the expected value “H” at the referencestrobe pulse. The first coincidence of the decision result the expectedvalue “H” means the detection of the timing of the reference calibrationpulse, and the delay of the variable delay circuit DY2 is fixed whichprovided the timing of the reference strobe pulse at that time. Forexample, as will be described later on with reference to FIG. 8, in thecase of controlling the delay of the variable delay circuit D2 indigital value, the digital value of its phase (delay) is written in adelay circuit DY2 setting memory (not shown) and the delay circuit DY2is set at the value written in the memory.

A description will be given below of a timing calibration method for thepath of the driver DR and a timing calibration method for the path ofthe comparator CP in the pin electronics 130. Prior to the calibratingoperation described below, it is necessary to calibrate the outputtiming of the reference driver DR-RF and the input timing of thereference comparator CP-RF that are mounted in the probe 300. Thisrequirement can be met simply by calibrating the one timing with respectto the other chosen as reference calibration timing.

For example, in the case of choosing the reference driver DR-RF, acalibration pulse is output from the reference driver DR-RF and, in theexample of FIG. 2, the calibration pulse is applied directly to thereference comparator CP-RF, wherein the variable delay circuit DY2 (seeFIG. 1), which determines the delay time of the strobe pulse, iscontrolled so that the application of the strobe pulse is timed to theleading edge (a 50% position on the leading edge).

On the other hand, in the case of choosing the reference comparatorCP-RF, a calibration pulse is provided therefrom and the variable delaycircuit DY1 (see FIG. 1), which determines the delay time of thecalibration pulse, is controlled to time its leading edge (the 50%position on the leading edge) to the application of the strobe pulse.

In either case, the calibration establishes the desired timedrelationship between the output from the reference driver and the inputto the reference comparator, and this timing is used to calibrate thetiming of the drivers DR and capacitors CP mounted in the pinelectronics 130 described below.

A description will be given first of how to calibrate the comparators CPmounted in the pin electronics 130. In this instance, the timing/patterngenerator 110 repeatedly outputs a reference calibration pulse PAdepicted in FIG. 3B onto the reference calibration pulse supply line 304with the test cycle period TS_(RAT) depicted in FIG. 3A. The referencecalibration pulse PA (FIG. 3B) is provided via the cable 301 to theprobe 300, thence to the test head 200 via the reference driver DR-RFmounted in the probe 300 and the spring contact 303, and thence to aselected one of the comparators CP of the pin electronics 130.

The comparator CP compares the calibration pulse with a referencevoltage VREF while shifting the phase of the strobe pulse STB for eachtest cycle by incrementing (or decrementing) the delay time of avariable delay circuit DY4 or DY6 by a fixed value (FIG. 3C), therebydetermining the phase (the amount of delay) of a strobe pulse STR-J inwhich the logical value of the comparison result reverses. As the resultof this, the delay time J of the strobe pulse STB that is provided tothe comparator CP (that is, the comparison timing of the comparator CP)is correctly calibrated so that the timing J of the calibration pulse PAmeasured by the comparator CP (i.e., the timing J at which the comparedoutput from the comparator CP (FIG. 3D) reverses when the value of thereference voltage VREF is at a 50% position of the amplitude of thecalibration pulse to which the value of the reference voltage VREF isset) coincides with the timing t of the reference calibration pulse PA(t=J). In this way the calibration of the comparator CP is performed. Inthis case, the decision as to whether the reference voltage is at the50% position of the amplitude of the calibration pulse may be madedepending on whether the probabilities of the comparator output goinghigh and low are 50% as the result of repeated decision within a certainperiod.

Next, a description will be given of how to calibrate each drivermounted in the pin electronics 130. In this instance, the timing/patterngenerator 110 repeatedly supplies calibration pulses of the same phasevia variable delay circuits DY3 and DY5 to the drivers DR for each testcycle. Each driver DR sends the calibration pulse to the test head 200.

In the test head 200 the probe 300 captures the calibration pulse thatis sent from the driver DR to be calibrated via an electrical pad formedon the contact board 204. The result of comparison between thecalibration pulse captured by the probe 300 and the reference voltage iscaptured by the calibrated reference comparator CP-RF in the probe 300at the timing of the reference strobe pulse set in the reference phase.By setting the delay time of the variable delay circuit DY3 or DY5 sothat the logical decision result of the timing decision device 140reverses when the timing of application of the reference strobe pulseis, for example, at a 50% position on the leading edge of thecalibration pulse, the timing calibration of the path of the driver DRis completed. The decision as to whether the reference voltage is at the50% position on the leading edge of the calibration pulse may be madedepending on whether the probabilities of the comparator output goinghigh and low are 50%.

FIG. 4 illustrates another embodiment of the present invention, in whichblocks 110, 120, 130 and 140 are identical in configuration with thecorresponding blocks in FIG. 1. In the timing calibration method of theFIG. 4 embodiment: a reference pin P-RF to which reference timing isprovided is determined for each IC socket (simply by choosing any one ofthe pins of the IC socket as the reference pin); the probe 300 isbrought into contact with that one of the contact pads on the contactboard 204 which corresponds to the reference pin P-RF (which contact padis identified by the same reference character P-RF as that of thereference pin), then the calibration pulse is provided via the referencepin P-RF to the probe 300 from that one of the drivers DR of the pinelectronics 130 which corresponds to the reference pin, then the timingof the calibration pulse is measured by the reference comparator CP-RFof the probe 300, and the timing thus measured is determined asreference timing (that is, the timing of the reference strobe pulse isdetermined by controlling the delay circuit DY2). Next, the delay timeof the variable delay circuit corresponding to each driver is controlledso that the timing of the calibration pulse provided to the probe 300from the driver coincides with the input timing of the referencecomparator CP-RF for each pin. The timing of the reference calibrationpulse that is applied to the reference driver DR-RF may be determined byadding the input timing of the reference comparator CP-RF with thepremeasured phase difference between the reference comparator and thereference driver. The timing thus defined is determined as referencetiming, and the reference calibration pulse is applied from the probe300 to each of the other pins to calibrate the input timing of thecorresponding comparator CP by the variable delay circuit DY4 or DY6.

In the case of adopting this calibration method, for example, when thedriver-associated path of the pin determined as the reference pin P-RFis used as the reference, delay times of drivers of the other pins arecalibrated to the initial delay time of the driver DR of the referencepin. Further, the input timing of the comparator of each pin is alsocalibrated to the delay time of the driver DR of the pin initiallydetermined as the reference pin, with the result that the delay times ofthe both driver- and comparator-associated paths of the respective pinsin the IC socket concerned are set to be the same.

Even if there is an error in the delay time of the driver-associatedpath of the reference pin in each IC socket, the error will not everaffect IC testing. That is, if there is no phase difference between thepins under test, such an error exerts no influence on the test. What iscalled for is to provide the same timing for test patterns from driversat respective pin positions of the IC under test and the same timing forcapturing the response signals by the comparators at the pin positions;the magnitude of the phases (delays) of the test patterns applied fromthe drivers and the comparator input timing does not matter.Accordingly, it is possible to determine the driver timing relative toarbitrary fixed timing and the comparator timing relative to arbitraryfixed timing without determining any particular reference pin.

For example, the timing of the reference calibration pulse and thetiming of the reference strobe pulse are fixed at arbitrary values bythe delay circuits DY1 and DY2, and the delay circuits DY3 and DY5 areadjusted so that the calibration pulse from each driver of the pinelectronics 130 is timed to the reference comparator CP-RF. As regardsthe comparator, the delay times of the variable delay circuits DY4 andDY6 are adjusted so that the input timing of each comparator of the pinelectronics 130 (the strobe pulse timing) is made to coincide with thetiming of the reference calibration pulse applied to each pin from thereference driver DR-RF.

The FIG. 4 embodiment is shown to have a construction in which twoprobes 300A and 300B are mounted on the same automatic positioningdevice 400 and are simultaneously driven to perform the timingcalibration of two IC socket at the same time. Reference numeral 150denotes a calibration controller.

FIG. 5 illustrates another example of the probe 300 in each embodimentdescribed above. The same line is shared for the reference strobe pulsesupply line 306 and the reference calibration supply line 304 to theprobe 300, and the relay switches RL2 and RL3 are selectively changedover for the strobe pulse application and for the calibration pulseapplication. Further, the variable delay circuits DY1 and DY2 in thecalibration controller 140 in FIG. 1 are placed in the probe 300, andthe temperature in the probe 300 is kept constant. That is, in thisexample the variable delay circuit DY1 for applying the referencecalibration pulse to the reference driver DR-RF, the variable delaycircuit DY2 for applying the reference strobe pulse to a D flip-flopthat captures the comparison decision result of the reference comparatorCP-RF, and a variable delay circuit DYO for delaying output signals fromthe both delay circuit by the same time interval are mounted in theprobe 300; these variable delay circuits DYO, DY1 and DY2, the referencedriver DR-RF and the reference comparator CP-RF and the D flip-flop areplaced in a constant temperature chamber 160 and are held in aconstant-temperature environment so as to suppress delay time variationsby temperature changes. Reference numeral 161 denotes a temperaturecontroller for controlling the temperature in the constant temperaturechamber 160 to be constant; 162 denotes, for example, a heater forheating the inside of the constant temperature chamber; and 163 denotesa temperature sensor for detecting the temperature in the constanttemperature chamber.

Reference numeral 164 denotes a D/A converter. The D/A converter 164 issupplied with a digital set value from the IC tester 100 and outputsvoltages VIH and VIL for setting the amplitude value of the pulse thatthe reference driver DR-RF and a control signal that is provided to anadjustment circuit 165 for adjusting the delay time difference betweenthe rise and fall of the detection pulse that the reference comparatorCP-RF outputs. That is, the adjustment circuit 165 sets current valuesof positive and negative side constant current circuits to adjust idlingcurrents of the circuit that turns ON upon rise of the detection pulseand the circuit that turns ON upon fall of the detection pulse, therebyadjusting the delay times of the leading and trailing edges of thedetection pulse to be equal to each other.

Reference numeral 166 denotes a relay control circuit for controllingthe relays RL1, RL2 and RL3. Reference numeral 167 a signal take-outterminal that is used in the case of monitoring the waveform of a signalthat is applied to the spring contact 303. With an oscilloscopeconnected to this signal output terminal, it is possible to monitor thesignal waveform.

In the FIG. 5 and preceding embodiments the output terminal of thereference driver DR-RF and the input terminal of the referencecomparator CP-RF mounted in the probe 300 are directly connected insidethe probe 300, but in this instance, since the signal input from thecommon spring contact 303 is branched at the branch point to supply tothe driver and the comparator, reflections occurs at the branch point,likely degrading the signal waveform.

In the case of applying the calibration pulse from the reference driverDR-RF to the reference comparator CP-RF to calibrate their timing, thecalibration is performed without including the time of signalpropagation to the extremity of the spring contact 303, incurring thepossibility that an error occurs accordingly.

For the reasons given above, in the FIG. 6 embodiment of FIG. 6, theoutput terminal of the reference driver DR-RF and the input terminalCP-RF are connected to separately provided spring contacts 303A and303B, which are brought into contact with the contact board 204 toperform calibration.

Accordingly, in this case, for example, as depicted in FIG. 7, a shortpad is placed at an arbitrary position on the contact board 204; thespring contacts 303A and 303B are contacted with the contact board 204to short their tips, and in this state the reference driver DR-RF andthe reference comparator CP-RF mounted on the probe 300 are calibrated.

Accordingly, since the FIG. 6 embodiment has no branch points at theoutput side of the reference driver DR-RF and the input side of thereference comparator CP-RF, no reflections occur and signal waveformwill not deteriorate.

Moreover, since the calibration of the reference driver DR-RF and thereference comparator CP-RF is performed including the extremities of thespring contacts 303A and 303B, the condition for this calibrationcoincides with that for the calibration of the driver DR and thecomparator CP on the pin electronics 130 that is carried out bycontacting the tips of the spring contacts 303A and 303B with thecontact board 204—this also serves to increase the calibration accuracy.

While in the embodiments of FIGS. 5 and 6 the temperature controller161, the D/A converter 164 and the relay control circuit 166 are mountedin the probe 300, it will easily be seen that they need not always to bemounted in the probe 300 but may also be mounted in the calibrationcontroller 150 depicted in FIG. 4.

FIG. 8 illustrates a concrete example of the calibration controller 140shown in FIG. 4. The calibration controller 140 of this examplecomprises a calibration cycle controller CALCON, variable delay circuitsDY1 and DY2, and a timing decision device 150 that decides whether thetiming of a signal for input to the reference comparator CP-RF coincideswith the timing of the strobe pulse STB.

The calibration cycle controller CALCON generates a control signal fordetermining the test cycle in which to perform calibration. The variabledelay circuits DY1 and DY2 are each composed of an integral delay timegenerating part M, a fractional delay time generating part PS and a gateG.

The integral delay time generating part M can be formed, for example, bya shift register and a selector for selectively taking out the outputsof respective stages of the shift register. The rate clock RAT, whichdefines the test cycle TS, is delayed by the shift register insynchronism with the period of a reference clock RFL, and the delayedrate clock RAT is taken out by the selector from that one of the stagesthat outputs the rate clock RAT after the time corresponding to anintegral multiple of the reference clock RFL in set delay data DAT1 orDAT2, and this delayed rate clock RAT is provided as a gate signal toone input terminal of the gate G.

The fractional delay time generating part PS is formed by a circuit thatphase-shifts the reference clock RFL at high resolution, and generates apulse train with a delay time (phase shift amount) corresponding to afractional value smaller than one period of the reference clock RFL inthe delay data DAT1 and DAT2.

The gate G extracts, by the gate signal from the integral delay timegenerating part M, the corresponding pulse in the pulse train generatedby the fractional delay time generating part PS, and outputs acalibration pulse CALP and a strobe pulse STB delayed by time intervalscorresponding to the delay data DAT1 and DAT2, respectively.

FIG. 9 shows how the above operations are carried out. FIG. 9A shows thereference clock RFL and FIG. 9B the rate clock RAT. The integral delaytime generating part M generates an integral delay pulse (FIG. 9C) bydelaying the rate clock RAT by a time interval corresponding to anintegral multiple (3T in the illustrated example) of one period T of thereference clock RFL.

This integral delayed pulse and a fractional delay pulse (FIG. 9E) areinput to the gate G1 or G2, wherein the fractional delay pulse isextracted by the integral delay pulse to thereby obtain a pulse (FIG.9F) of a delay time 3T+φ that a fractional delay amount φ is added tothe integral delay time 3T. This pulse is provided as the calibrationpulse CALP or strobe pulse STB to the reference driver DR-RF orreference comparator CP-RF mounted in the probe 300.

Incidentally, the FIG. 9 example shows the case where the integral delaypulse depicted in FIG. 9C is synchronized with the fractional delaypulse and to adjust their phases (FIG. 9D) to gate the fractional delaypulse at the central portion of the integral delay pulse in the gates G1and G2.

FIG. 10 depicts an embodiment of the fractional delay time generatingpart PS. This embodiment is shown to comprise a voltage-controlledoscillator VCO, a pair of frequency dividers DVD1 and DVD2, a phasecomparator PHD, an analog adder ADD, a low-pass filter FIL, and a D/Aconverter DAC that provides a phase shift voltage VS to the analog adderADD.

This circuit constitutes a well-known phase-locked loop (PLL). Thereference clock RFL is applied to an input terminal Tin, and ifnecessary, it is frequency-divided and the frequency-divided output isfed to the one input terminal of the phase comparator PHD.

To the other input terminal of the phase comparator PHD is fed anoscillation signal of the voltage-controlled oscillator VCO and afterbeing frequency-divided by the frequency divider DVD2. The frequencydividers DVD1 and DVD2 have the same frequency dividing ratio.Accordingly, the frequencies of the input signals to the phasecomparator PHD is set at the same value, and the phase between thesignals of the same frequency is compared by the phase comparator PHD,and the phase compared output is provided to the one input terminal ofthe analog adder ADD.

To the other input terminal of the analog adder ADD is provided acontrol voltage VS from the D/A converter DAC for setting the fractionaldelay time. The low-pass filter FIL is connected to the output side ofthe analog adder ADD, and a voltage signal CV smoothed by the low-passfilter FIL is taken out, the voltage signal CV being applied to avoltage-controlled terminal of the voltage-controlled oscillator VCO tocontrol its oscillation phase.

This phase-locked loop PLL forms a closed feedback loop so that theoutput from the analog adder ADD becomes zero. Accordingly, this phaselocked loop operates so that the output from the phase comparator PHDand the output from the D/A converter DAC are opposite in polarity buthave the same value.

That is, when the output from the D/A converter is 0 V, thevoltage-controlled oscillator VCO outputs a pulse train of the samephase as the reference clock RFL and the output from the phasecomparator PHD also becomes 0 V. For example, when the output from theD/A converter DAC is 1 mV, the phase comparator PHD outputs −1 mV andthe voltage-controlled oscillator VCO is shifted to a phase (laggingphase) in which to generate a phase compared output of −1 mV from thereference clock RFL.

Accordingly, by inputting from the D/A converter DAC a voltage signalthat changes by steps of +1 mV, the pulse train that thevoltage-controlled oscillator VCO is phase-shifted each time by anamount corresponding to −1 mV resolution. Assume that the transfercoefficient of the phase comparator PHD is, for example, 1 PS/1 mV; byinputting from the D/A converter DAC a signal that increases by steps of+1 mV, the phase of the pulse train that the voltage-controlledoscillator VCO oscillates is shifted by steps of 1 PS in the directionof delay.

Assuming that the D/A converter DAC is, for example, a 12-bit D/Aconverter and that the output resolution of the least significant bit is1 mV, it outputs a voltage in the range of 1 mV to 4096 mV. Accordingly,the phase of the pulse train that the voltage-controlled oscillator VCOoscillates can be delayed from the same phase as the reference clock RFLto a phase lagging 4096 PS behind the reference clock.

With the use of the phase locked loop, the phase of the pulse train thatthe voltage-controlled oscillator VCO generates can be delayed over awide range, and a pulse in the pulse train specified by the integraldelay time is extracted as the calibration pulse CALP or strobe pulseSTB; hence it is used as the calibration pulse CAL or strobe pulse STBwhile retaining high resolution. Accordingly, it is possible to obtainthe calibration pulse CALP or strobe pulse of high timing accuracy.

Effect of the Invention

As described above, the present invention utilizes the function ofsetting the signal generating timing at prescribed timing and thefunction of measuring the input signal, which the IC tester 100inherently possesses; hence, the invention permits low-cost fabricationof the calibration device. In addition, since the driver- andcomparator-associated paths are both calibrated using direct waves, thecalibration accuracy is high. Thus, the present invention offers alow-cost and highly accurate IC tester.

What is claimed is:
 1. An integrated circuit (IC) tester testing an ICunder test which has a calibration function, wherein the IC testercomprises: a timing/pattern generator; drivers each provided incorrespondence with a respective pin of an IC socket on which the ICunder test is mounted; comparators each provided in correspondence witha respective pin of the IC socket; driver variable delay circuits eachprovided in series with and in correspondence with a respective driver;strobe variable delay circuits each provided in a signal path of astrobe pulse for a respective comparator; a probe including a referencedriver and a reference comparator; and calibration control meansincluding a reference driver variable delay circuit and a referencestrobe variable delay circuit; wherein to perform the calibrationfunction, (a) the timing/pattern generator is operable to supply areference strobe pulse having a reference timing to the referencecomparator of the probe, a reference calibration pulse having thereference timing of the reference strobe pulse to the reference driverof the probe, strobe pulses having the same timing to each other to saidcomparators, respectively, and calibration pulses having the same phaseto each other to said drivers, respectively, (b) the probe is operableto contact selectively respective pins of the IC socket so that, duringcalibration of the comparators, the comparator connected to a selectedpin of the IC socket captures a logical value of the referencecalibration pulse supplied to the selected pin of the IC socket from thereference driver at a timing of the strobe pulse supplied thereto fromthe timing/pattern generator through a respective strobe variable delaycircuit, and so that, during calibration of the drivers, the referencecomparator captures the logical value of the calibration pulse appliedto the selected pin of the IC socket through a respective drivervariable delay circuit from a driver at the reference timing of thereference strobe pulse, and (c) the calibration control means isoperable to control said driver variable delay circuit so that the phaseof said calibration pulse applied to the selected pin of said IC socketfrom said driver coincides with the reference timing of said referencestrobe pulse, and said strobe variable delay circuit so that the timingof said reference calibration pulse to be applied to the selected pin ofsaid IC socket coincides with the timing of the strobe pulse to beapplied to the comparator corresponding to said selected pin.
 2. Anintegrated circuit (IC) tester which has drivers each connected to arespective pin of an IC socket on which an IC under test is placed, forapplying a test pattern signal to an input terminal of the IC undertest, and comparators each provided in correspondence with a respectivepin of the IC socket for capturing a logical value of a response outputsignal obtained from an output terminal of the IC under test, anddecides whether the response output signal coincides with apredetermined expected value to determine whether said IC under test isa defective article, wherein said IC tester has a calibration functionand comprises: a probe for selectively contacting respective pins ofsaid IC socket; a reference comparator mounted in said probe forcapturing respective calibration pulses applied to respective pins ofsaid IC socket while in contact with said probe at a reference timing ofa reference strobe pulse; a reference driver mounted in said probe forapplying reference calibration pulses to respective pins of said ICsocket while in contact with said probe; driver variable delay circuitseach provided in a signal path of a respective driver for adjusting adelay time of the calibration pulse to be applied through saidrespective driver to a corresponding pin of said IC socket; strobevariable delay circuits each provided in a signal path of a strobe pulseto be applied to a respective comparator for adjusting a delay time ofsaid strobe pulse; and calibration control means for calibrating thedrivers by comparing a logical value of the calibration pulse capturedby said reference comparator with an expected value, and controllingeach driver variable delay circuit so that phases of calibration pulsesapplied to respective pins of said IC socket from each of said driverscoincide with the reference timing of said reference strobe pulse, andfor calibrating the comparators by controlling each said strobe variabledelay circuit so that the timings of strobe pulses to be applied to therespective comparators coincide with the timing of said referencecalibration pulse to be applied to respective pins of said IC socket. 3.The IC tester as claimed in claim 2, which further comprises: areference calibration pulse variable delay circuit provided in thesignal path of said reference driver for adjusting the timing of saidreference calibration pulse; and a reference strobe pulse variable delaycircuit provided in the signal path of said reference strobe pulse foradjusting the timing of said reference strobe pulse.
 4. The IC tester asclaimed in claim 3, wherein said probe is supported by an automaticpositioning device movable in X, Y and Z directions above a test headwith said IC socket placed thereon, and automatically contacts each pinof said IC socket to perform timing calibration of driver- andcomparator-associated signal paths.
 5. The IC tester as claimed in claim4, wherein a plurality of such probes are provided, which areautomatically contacted with a plurality of IC sockets, respectively, tosimultaneously perform timing calibration of driver- andcomparator-associated signal paths connected to said IC sockets.
 6. TheIC tester as claimed in claim 4, which has a construction in which anoutput terminal of the reference driver and an input terminal of thereference comparator mounted in said probe are connected to separatelyprovided contacts and the output of the reference driver and the inputof the reference comparator are contacted with each pin of said ICsocket through said independent contacts to perform timing calibration.7. The IC tester as claimed in claim 6, which has a construction inwhich a short pad is provided on the surface of movement of saidcontacts; the contact connected to the output terminal of said referencedriver and the contact connected to the input terminal of said referencecomparator are contacted with said short pad to short them; and thereference calibration pulse from said reference driver is fed via saidshort pad to said reference comparator to calibrate the timing of eitherone of said reference driver and said reference comparator.
 8. The ICtester as claimed in any one of claims 2 to 7, wherein there is providedmeans for adjusting the delay time difference between rise and fall ofdetection pulses that are output by said reference comparator.
 9. The ICtester as claimed in claim 7, wherein said reference calibration pulsevariable delay circuit and said reference strobe pulse variable delaycircuit each comprises: a fractional delay time generating part formedby a phase locked loop and adding means for finely shifting oscillationphase of a voltage-controlled oscillator forming the phase locked loop;and an integral delay time generating part for generating a delay timethat is an integral multiple of pulse period of a pulse train of areference frequency that is applied to said phase locked loop.
 10. TheIC tester as claimed in any one of claims 3 to 7, wherein said probe hasmounted therein a constant temperature chamber, in which said referencedriver, said reference comparator, said reference calibration pulsevariable delay circuit and said reference strobe pulse variable delaycircuit are mounted to keep temperature constant.
 11. A timingcalibration method for an integrated circuit (IC) tester that comprisesan IC socket having a plurality of pins to be calibrated, a plurality ofcomparators each connected to a respective one of the pins, and a probeincluding a reference driver, said method comprising the steps of: (a)applying a reference calibration pulse from said reference driver ofsaid probe to a first selected pin of said IC socket while in contactwith the probe; (b) capturing said reference calibration pulse appliedfrom said reference driver to said first selected pin by one comparatorof said plurality of comparators that is connected to said firstselected pin at the timing of a strobe pulse that is provided to saidone comparator; (c) calculating a deviation between the timing of saidreference calibration pulse and the timing of said strobe pulse for saidone comparator; (d) adjusting the delay time of a timing calibratingvariable delay circuit provided in a signal path of said strobe pulsefor said one comparator so that said deviation for said one comparatorbecomes a predetermined value for comparator; and (e) repeating steps(a) to (d) for a different first selected pin until the deviations forrespective comparators become the same predetermined value forcomparator to thereby calibrate said plurality of comparators.
 12. Thetiming calibration method as claimed in claim 11, which furthercomprises a step of pre-adjusting the delay time of a timing calibratingvariable delay circuit for the reference driver provided in the signalpath of said reference calibration pulse so that the timing of thereference calibration pulse from said reference driver coincides withthe timing of a strobe pulse that is provided to a comparator connectedto a predetermined reference pin of said IC socket.
 13. The timingcalibration method according to claim 11, wherein the integrated circuit(IC) tester further comprises a plurality of drivers each connected to arespective one of said pins and said probe further includes a referencedriver, said method further comprising the steps of: (f) applying acalibration pulse from one driver of the plurality of drivers to asecond selected pin of said IC socket that is connected to said onedriver while in contact with the probe; (g) capturing said calibrationpulse from said one driver through said second selected pin by saidreference comparator of said probe at the timing of a reference strobepulse that is provided to said reference comparator; (h) calculating adeviation between the timing of said calibration pulse from said onedriver and the timing of said reference strobe pulse; (i) adjusting thedelay time of a timing calibrating variable delay circuit provided in asignal path of said one driver so that said deviation for said onedriver becomes a predetermined value for driver; (j) repeating steps (f)to (i) for a different second selected pin until the deviations forrespective drivers become the same predetermined value for driver tothereby calibrate said plurality of drivers.
 14. The timing calibrationmethod as claimed in claim 13, wherein said first selected pin and saidsecond selected pin are the same pin.
 15. The timing calibration methodas claimed in claim 13, which further comprises pre-adjusting the delaytime of a timing calibrating variable delay circuit for the referencecomparator provided in the signal path of said reference strobe pulse sothat the timing of said reference strobe pulse coincides with the timingof a calibration pulse provided from a predetermined reference pin ofsaid IC socket.
 16. The timing calibration method as claimed in claim13, which further comprises pre-adjusting the delay time of a timingcalibrating variable delay circuit for the reference driver provided inthe signal path of said reference calibration pulse so that the timingof the reference calibration pulse from said reference driver coincideswith the timing of a strobe pulse that is provided to a comparatorconnected to a predetermined reference pin of said IC socket.
 17. Thetiming calibration method as claimed in claim 13, which furthercomprises adjusting either the delay time of a timing calibratingvariable delay circuit provided in the signal path of said referencecalibration pulse or the delay time of a timing calibrating variabledelay circuit provided in the signal path of said reference strobe pulseso that the timing of the reference calibration pulse from saidreference driver coincides with the timing of the reference strobe pulsethat is provided to said reference comparator.
 18. An integrated circuit(IC) tester having an IC testing function for testing an IC under testand a calibration function, comprising: comparators each provided incorrespondence with a respective pin of an IC socket on which the ICunder test is placed for capturing a logical value of a response outputsignal obtained from an output terminal of the IC under test at a timingof a strobe pulse during the IC testing function; a probe forselectively contacting the pins of said IC socket one after another; areference driver mounted in said probe for applying a referencecalibration pulse to a selected pin of said IC socket; strobe variabledelay circuits, wherein each strobe variable delay circuit is providedin a path of the strobe pulse to be applied to each of said comparators,for adjusting a delay time of said strobe pulse; and calibration controlmeans for controlling each of said strobe variable delay circuits sothat the timing of the strobe pulses to be applied to respectivecomparators coincide with the timing of said reference calibration pulseto be applied to respective pins of said IC socket.